These full adders perform the addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

NOTE: HC version is the high speed CMOS version which we may supply due to availability. It is fully compatible with LS version and one to one replaceable (not vice versa as HC version has more features)

Datasheet:

LS: https://www.ti.com/lit/ds/symlink/sn74ls283.pdf

HC: https://www.renesas.com/in/en/document/dst/hd74hc83-datasheet