The 74LS147 is a Priority Encoder. It provides priority decoding of the inputs to ensure that only the highest order data line is encoded. The device has data inputs and outputs which are active at the low logic level. It encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level.

NOTE: HC version is the high speed CMOS version which we may supply due to availability. It is fully compatible with LS version and one to one replaceable (not vice versa as HC version has more features)

Datasheet:

LS: https://www.ti.com/lit/ds/symlink/sn54ls148.pdf

HC: https://www.ti.com/lit/ds/symlink/cd74hct147.pdf