74LS138 is a member from ‘74xx’family of TTL logic gates. The chip is designed for decoding or de-multiplexing applications and comes with 3 inputs to 8 output setup. The design is also made for the chip to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high performance memory systems these decoders can be used to minimize the effects of system decoding. The three enable pins of chip (in which Two active-low and one active-high) reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter.

74LS138 is used in de-multiplexing applications by using enable pin as data input pin. Also the chip inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

NOTE: HC version is the high speed CMOS version which we may supply due to availability. It is fully compatible with LS version and one to one replaceable (not vice versa as HC version has more features)

Datasheet:

LS: https://www.ti.com/lit/ds/symlink/sn54ls138-sp.pdf

HC: https://docs.rs-online.com/9cbe/0900766b812cd41c.pdf