CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode.

If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage.

Features:

• Medium-speed operation - fCL = 8 NHz typ. at 10 V
• Synchronous internal carry propagation
• Reset and Preset capability
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  1 V at VDD = 5 V
  2 V at VDD = 10 V
  2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Applications:
  • Up/Down difference counting
  • Multistage synchronous counting
  • Multistage ripple counting
  • Synchronous frequency divider

Package: PDIP-20

Datasheet: Datasheet