The 74LS595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

NOTE: HC version is the high speed CMOS version which we may supply due to availability. It is fully compatible with LS version and one to one replaceable (not vice versa as HC version has more features)

Datasheet:

LS: https://www.ti.com/lit/ds/symlink/sn74ls595.pdf

HC: https://www.ti.com/lit/ds/symlink/sn74hc595.pdf